During the RAPIDO workshop some relevant personalities of our community will held a keynote.
Abstract Text Analytics is the process of extracting valuable information and insight from large scale unstructured text data. IBM’s SystemT text analytics software is an essential part of IBM’s Big Data analytics platforms, such as InfoSphere BigInsights and Infosphere Streams. SystemT couples a declarative rule language with a modular runtime based on relational algebra, augmented with special operators for information extraction, such as regular expressions and dictionaries. This approach improves the expressive power of the rule language and enables cost-based rule optimization. A key contribution of our work is a hardware compiler that can transform complete text analytics rules to data flow pipelines realized on reconfigurable platforms, such as Field Programmable Gate Arrays (FPGAs). Our hardware compiler leverages the nature of text processing by parallelizing regular expression and dictionary matching operations and by executing the subsequent relational operations in a streaming fashion. An integral part of our hardware compiler is a regular expression compiler, which produces reconfigurable nondeterministic finite state machine implementations that support advanced regular expression matching features required by text analytics systems, such as start and end offset reporting, capturing groups, and leftmost matching. The hardware accelerators that are automatically generated by our compiler achieve an order of magnitude improvement of the processing rates and the energy efficiency with respect to the multi-threaded software implementation of SystemT.
Short Bio Kubilay Atasu received his B.Sc. and Ph.D. degrees, both in computer engineering, from Bogazici University, Istanbul, respectively in 2000 and 2007. He also has a M.Eng. Degree from ALaRI, University of Lugano. From 2002 to 2003, he was a research assistant at the Swiss Federal Institute of Technology Lausanne. Between 2005 and 2008 he was a research associate at the Department of Computing, Imperial College London. In summer 2006, he was a visiting researcher at Stanford University. Since May 2008, Kubilay is with IBM Research - Zurich. His research interests include design of hardware accelerators and use of hardware/software co-design and reconfigurable computing techniques to improve the computational efficiency, especially, of Big Data applications. Kubilay Atasu was the recipient of a best paper award at the Design Automation Conference (DAC) in 2003, and at the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) in 2008 and 2014. He was a program co-chair of ASAP 2013 and the general chair of ASAP 2014. He has also served in the program committees of DATE, FPL, and FPT conferences.
Abstract Benchmarks capture the essence of many important real-world applications and allow performance, and power analysis while developing new systems. Synthetic benchmarks are a miniaturized form of benchmarks that allow high simulation speeds and act as proxies to proprietary applications. Development of new parallel applications and benchmarks exploit parallel software patterns. For the first time, we leverage these patterns in developing synthetic benchmarks for multicore systems. We developed an automated tool, named MINIME, complete with characterization and synthesis components and performed experiments on PARSEC, Rodinia, and EEMBC benchmarks. Our results show that the synthetic benchmarks and the real applications are similar with respect to various metrics.
Short Bio Alper Sen received the PhD degree in Electrical and Computer Engineering from the University of Texas at Austin in 2004. He is currently an Associate Professor with the Department of Computer Engineering, Bogazici University, Istanbul, Turkey. He was a Member of Technical Staff in the Design Technology Organization at Freescale Semiconductor Inc., Austin and also an Adjunct Professor at the University of Texas at Austin. He is the recipient of The Turkish Academy of Sciences Young Scientist Award. His current research interests include verification of hardware and software systems, parallel programming, embedded and multicore systems, and system-level designs. He is a senior member of the IEEE.
Abstract There are today several methodologies and tools to program (heterogeneous) Multi-Processor Systems-on-Chip (MPSoCs). Depending on the development stage of the actual hardware, these programming frameworks have to make use of different technologies to estimate performance and other metrics of software. In this presentation we introduce such a programming framework and provide details of different estimation methods, including measurement-aided, simulation and emulation. Furthermore, we describe current approaches for accelerating platform simulation as well as new use cases for virtual prototypes, such as parallel software debugging.
Short Bio Jeronimo Castrillon received the Electronics Engineering degree with honors from the Pontificia Bolivariana University in Colombia in 2004, the master degree from the ALaRI Institute in Switzerland in 2006 and the Ph.D. degree (Dr.-Ing.) on Electric Engineering and Information Technology with honors from the RWTH Aachen University in Germany in 2013. From early 2009 to April 2013 Dr. Castrillon was the chief engineer of the chair for Software for Systems on Silicon at the RWTH Aachen University, where he was enrolled as research staff since late 2006. From April 2013 to April 2014 Dr. Castrillon was senior scientific staff in the same institution. In June 2014, Dr. Castrillon joined the department of computer science of the TU Dresden as professor for compiler construction in the context of the German excellence cluster “Center for Advancing Electronics Dresden” (CfAED). His research interests lie on methodologies, languages, tools and algorithms for programming complex computing systems. In late 2014 he co-founded Silexica Software Solutions GmbH, a startup that provides programming tools for embedded multicore architectures.